Summary: Bullish on high-end ABF substrates amid CPO/AI GPU buildout; TSMC CPO ramp and NVIDIA Vera Rubin drive 5–10x ABF consumption growth, supply-demand tight long-term.

▶ ABF Substrates Emerge as a Key Battleground in CPO Integration

- Amid explosive growth in ultra-high-speed transmission demand for AI data centers, TSMC's Co-Packaged Optics (CPO) strategy is also moving up a level.

- TSMC recently disclosed that its "COUPE on Substrate" solution — which integrates a Compact Universal Photonic Engine (COUPE) — is on track to enter mass production in 2H 2026.

- The industry reads this as more than just an optical communication upgrade. It signals that AI supply chain competition is expanding beyond advanced process and advanced packaging into the ABF substrate and CPO integration domain.

- As NVIDIA's next-generation Vera Rubin platform continues to raise the integration level across AI GPUs, HBM, and ultra-high-speed networking interconnects, the importance of high-end substrates is set to grow rapidly.

- In particular, semiconductor industry participants note that if CPO establishes itself as the mainstream AI server architecture going forward, NVIDIA may move to preemptively secure high-end ABF substrate capacity through long-term agreements (LTAs), prepayments, and strategic partnerships.

- This would be a strategic move aimed at preventing a repeat of the past CoWoS and HBM supply shortages.

- In addition, compared with conventional CPU substrates, substrates for AI GPUs and ASICs feature significantly larger area and substantially higher layer counts, expanding ABF material consumption by 5–10x.

- With demand for AI GPUs, ASICs, and high-end networking chips continuing to grow, the supply-demand structure for high-end ABF substrates is expected to remain tight for an extended period.

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https://t.co/brRfdlWTzA


TSMC's Co-Packaged Optics (CPO) strategy is also moving up a level… COUPE on Substrate solution… on track to enter mass production in 2H 2026

structural marker; pre-classified as canonical yfinance ticker


NVIDIA's next-generation Vera Rubin platform continues to raise the integration level across AI GPUs, HBM, and ultra-high-speed networking interconnects


some idiots are selling because they think TSMC's margins peaked in Q1

Summary: Implicitly bullish TSMC; dismisses sellers who think margins peaked in Q1 as wrong.

I heard some idiots are selling because they think TSMC’s margins peaked in Q1.


Summary: AI CPU DRAM demand (300–400GB per unit) on top of HBM extends DRAM supercycle into 2027; bullish MU, Samsung, SK Hynix.

AI CPUs Are Devouring DRAM — Memory 'Shortage' to Last Another Year

The memory industry has posted record-breaking results driven by commodity DRAM prices that have surged more than 100%, and with the proliferation of AI-purposed central processing units (CPUs) now coming into play, forecasts suggest the shortage will extend for another year.

Intel's recently unveiled "AI CPU" is expected to carry up to four times more commodity DRAM than previous generations. Combined with surging demand from graphics processing units (GPUs) that require high-capacity DRAM, observers expect the memory supply capacity of Samsung Electronics and SK hynix to fall short of demand.

According to industry sources on the 2nd, CPU manufacturers are pursuing the integration of 300–400GB of DRAM into AI CPUs. This is up to four times the overwhelming scale compared to typical CPU products (96–256GB).

CPUs Emerge as the 'AI Orchestrator'

The surge in high-capacity DRAM demand for AI CPUs is tied to the AI industry's pivot toward an inference-centric structure. Whereas AI inference was once limited to simple Q&A, it now serves as the "orchestrator" coordinating various agentic AIs.

The key in this process is "context memory." For a CPU to coordinate the entire workflow by referencing the outputs of each agentic AI, it must remember the content. This makes scaling up memory — the space for retention — essential.

Until now, AI data centers have built computing infrastructure centered on GPUs equipped with High Bandwidth Memory (HBM). Leveraging the GPU's strength in training AI on vast amounts of data simultaneously, the focus has been on "AI training." Server configurations accordingly followed an 8-GPU-to-1-CPU pattern. However, as the industry's center of gravity shifts toward inference, server configurations with substantially expanded CPU ratios are spreading.

In a recent earnings call, Intel executives explained: "In AI inference infrastructure, the computing structure has shifted to a CPU-to-GPU ratio of 1 to 4, and the trend is moving further toward 1 to 1."

After GPUs, CPUs Join the Memory Battle — Demand Snowballs

The competition for memory capacity has expanded from GPUs to CPUs, snowballing in scale. NVIDIA's next-generation AI chip "Vera Rubin" carries 288GB through 8 HBM stacks, while AMD's next-generation GPU MI400 boasts an even larger 432GB mammoth-class capacity.

Google's recently unveiled custom chip — the 8th-generation Tensor Processing Unit (TPU 8i) — is also slated to feature 288GB of HBM. Add to this Intel's AI CPU "Xeon" and AMD's "EPYC" beginning to use up to 400GB of high-capacity DDR5, and the memory shortage is expected to persist longer.

The market temperature is already being proven in spot prices. According to Kiwoom Securities, while the price of legacy DDR4 (16GB basis) plunged 16% in a single month in April, the spot price of DDR5 (16GB basis) — used in AI CPUs — rose 2.8% over the same period, maintaining its price premium.

An industry source said: "The current DRAM market is understood to be roughly 10 percentage points short of demand. With commodity DRAM demand surging on top of HBM, the supercycle is highly likely to extend from the previously expected 2026 into 2027."

$MU $DRAM

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https://t.co/XP6ENlQKbs


observers expect the memory supply capacity of Samsung Electronics and SK hynix to fall short of demand

Samsung Electronics listed on KOSPI as 005930.KS


Summary: Onto Innovation named as the most advanced player supplying hybrid bonding inspection tools to Samsung's mass production lines, with broader adoption expected through year-end.

industry='Semiconductor Equipment & Materials'

Samsung Electronics Introduces New Hybrid Bonding Inspection Equipment

Samsung Electronics has begun adopting new inspection equipment for hybrid bonding. Onto Innovation's inspection tools are reportedly being validated on mass production lines.

According to industry sources on the 31st, Samsung Electronics is in discussions or joint development with multiple companies possessing ultrasonic and X-ray-based non-destructive inspection (NDI) technologies. The primary objective is to detect micro-defects such as voids at hybrid bonding interfaces that are difficult to identify with conventional optical equipment. The inspection process also minimizes loss costs associated with expensive wafers and high-bandwidth memory (HBM).

The most advanced player is U.S.-based Onto Innovation. It has already established a joint development program (JDP) with Samsung Electronics for non-destructive inspection equipment and has supplied tools to mass production lines. The equipment utilizes laser-ultrasonic technology based on photoacoustic metrology. When a picosecond (one-trillionth of a second) ultra-short pulse pump laser is directed at the inspection target, the material undergoes momentary thermal expansion. This expansion generates ultrasonic waves that penetrate inward. These waves pass through optically opaque layers such as metal layers—which light cannot penetrate—and are reflected upon encountering underlying structures or voids. A probe laser then detects minute surface deformations to map the internal structure. This approach overcomes the limitations of conventional optical inspection and enables measurement of overlay alignment errors between upper and lower structures.

Domestic (Korean) companies are expected to see equipment adoption or JDP signings materialize as early as Q2. Some have already received bonding wafer samples from Samsung Electronics and completed performance testing. Bonding wafers refer to the output of the hybrid bonding process. Test results are reported to have been positive. Other companies are also in ongoing discussions with Samsung Electronics, preparing non-destructive inspection equipment for production lines.

An industry source noted, "Various departments within Samsung Electronics are in behind-the-scenes discussions with multiple equipment vendors," adding that "both TSV (through-silicon via) inspection and hybrid bonding interface inspection for HBM are being considered."

Samsung Electronics unveiled a video on hybrid bonding technology for HBM at NVIDIA's annual developer conference (GTC) 2026 this month. The industry expects Samsung to adopt hybrid bonding starting from next-generation HBM4E with 16 or more stacked layers. Last month, Samsung also presented a paper at the International Solid-State Circuits Conference (ISSCC) on fabricating 4F-square (4F²) DRAM using wafer-to-wafer (W2W) hybrid bonding. The approach applies a cell-over-periphery (COP) architecture to manufacture DRAM in a vertical channel transistor (VCT) structure—precisely stacking a periphery wafer and a cell array wafer on top of each other. Inspecting both of these next-generation memory types requires equipment capable of examining hybrid bonding interfaces.

Generally, qualification testing for back-end semiconductor equipment on production lines takes approximately six months. Considering this timeline, Samsung Electronics is expected to evaluate and compare inspection equipment performance from multiple vendors through the end of this year.

Hybrid bonding is an advanced packaging technology that directly connects copper (Cu) surfaces of two semiconductor dies when stacking and interconnecting chips. Unlike thermocompression (TC) bonding—primarily used in HBM manufacturing—it does not use micro bumps for chip-to-chip bonding. Compared to conventional soldering, hybrid bonding offers a larger bonding area and lower interfacial resistance, resulting in superior thermal dissipation and electrical characteristics.

$ONTO

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https://t.co/CT1pU4TimS


Summary: Intel's EMIB packaging technology being adopted by AWS Trainium and Google TPU programs via MediaTek; implied design-win tailwind for INTC.

I didn’t realize this, but it looks like AWS may be using EMIB for a lower-end version of Trainium through MediaTek.

Similar to the TPU v9 program handled by MediaTek, next-generation Trainium seems likely to use both EMIB and CoWoS.

$INTC